`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:23:53 07/02/2015 
// Design Name: 
// Module Name:    Etapa4 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Etapa4(
	input [31:0] salidaALU,//ta
	input zeroFlag,//ta
	input [31:0] salidaAdder,//ta
	input [4:0] salidaMux, //ta
	input [31:0] Data2,//ta
	input RegWrite,//ta
	input PCSrc1,//ta
	input MemRead1, //ta
	input [3:0] MemWrite1,//ta
	input MemToReg1,
	input [2:0] LoadOp1,//ta
	input clk, //ta
	output [31:0] salidaE4,
	output PCSrc,
	output [31:0] salidaAdder1,
	output [4:0] salidaMux1,
	output RegWrite1,
	output MemToReg,
	output [31:0] ALUdata
    );

wire [31:0] salidaMem;
assign PCSrc = PCSrc1 & zeroFlag;
assign salidaAdder1 = salidaAdder;
assign salidaMux1 = salidaMux; 
assign RegWrite1 = RegWrite;
assign MemToReg = MemToReg1;
assign ALUdata = salidaALU;

MemoriaDatos datos(
.clk(clk),
.enable(MemRead1),
.addr(salidaALU),
.write(MemWrite1),
.dataIn(Data2),
.dataOut(salidaMem)
);

LoadControlUnit nombre(
.in(salidaMem),
.out(salidaE4),
.ctrl(LoadOp1)
);

endmodule
